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PSoC
®
4: PSoC 4000 Family
Datasheet
Programmable System-on-Chip (PSoC
®
)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-89638 Rev. *E Revised May 26, 2015
General Description
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM
®
Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture. It is a combination of a microcontroller with
standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, and
general-purpose analog. PSoC 4000 products will be fully upward compatible with members of the PSoC 4 platform for new applica-
tions and design needs.
Features
32-bit MCU Subsystem
■ 16-MHz ARM Cortex-M0 CPU
■ Up to 16 KB of flash with Read Accelerator
■ Up to 2 KB of SRAM
Programmable Analog
■ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications
■ One low-power comparator with internal reference
Low Power 1.71-V to 5.5-V operation
■ Deep Sleep mode with wake-up on interrupt and I
2
C address
detect
Capacitive Sensing
■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) and water tolerance
■ Cypress-supplied software component makes capacitive
sensing design easy
■ Automatic hardware tuning (SmartSense™) over a sensor
range of 5 pF to 45 pF
Serial Communication
■ Multi-master I
2
C block with the ability to do address matching
during Deep Sleep and generate a wake-up on match
Timing and Pulse-Width Modulation
■ One 16-bit timer/counter/pulse-width modulator (TCPWM)
block
■ Center-aligned, Edge, and Pseudo-Random modes
■ Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 20 Programmable GPIO Pins
■ 28-pin SSOP, 24-pin QFN, 16-pin SOIC, 16-pin QFN, 16 ball
WLCSP, and 8-pin SOIC packages
■ GPIO pins on Ports 0, 1, and 2 can be CapSense or have other
functions
■ Drive modes, strengths, and slew rates are programmable
PSoC Creator Design Environment
■ Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■ Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
■ After schematic entry, development can be done with
ARM-based industry-standard development tools
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 7 Seite 8 Seite 11
- ・ Abmessungen des Paketumrisses on Seite 26 Seite 28
- ・ Teilenummerierungssystem on Seite 23
- ・ Blockdiagramm on Seite 4
- ・ Schweißen Temperatur on Seite 25
- ・ Beschreibung der Funktionen on Seite 1
- ・ Technische Daten on Seite 14 Seite 15 Seite 16 Seite 17 Seite 18
- ・ Anwendungsbereich on Seite 1
- ・ Elektrische Spezifikation on Seite 14
