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CY7B991
CY7B992
Programmable Skew Clock Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07138 Rev. *J Revised March 24, 2012
Programmable Skew Clock Buffer
Features
■ All output pair skew <100 ps typical (250 ps maximum)
■ 3.75 MHz to 80 MHz output operation
■ User selectable output functions
❐ Selectable skew to 18 ns
❐ Inverted and non-inverted
❐ Operation at 1⁄2 and 1⁄4 input frequency
❐ Operation at 2 × and 4 × input frequency (input as low as
3.75 MHz)
■ Zero input to output delay
■ 50% duty cycle outputs
■ Outputs drive 50 terminated lines
■ Low operating current
■ 32-pin PLCC/LCC package
■ Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buffers
(PSCB) offer user selectable control over system clock functions.
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high
performance computer systems. Each of the eight individual
drivers, arranged in four pairs of user controllable outputs, can
drive terminated transmission lines with impedances as low as
50. They can deliver minimal and specified output skews and
full swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output is hardwired to one of the nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency with outputs that skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and
transmission line delay effects. When this “zero delay” capability
of the PSCB is combined with the selectable output skew
functions, you can create output-to-output delays of up to ±12
time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that are multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
FILTER
PHASE
FREQ
DET
Logic Block Diagram
Verzeichnis
