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Altera Corporation 1
APEX II
Programmable Logic
Device Family
August 2002, ver. 3.0 Data Sheet
DS-APEXII-3.0
Features...
■ Programmable logic device (PLD) manufactured using a 0.15-µm all-
layer copper-metal fabrication process (up to eight layers of metal)
– 1-gigabit per second (Gbps) True-LVDS
TM
, LVPECL, pseudo
current mode logic (PCML), and HyperTransport
TM
interface
– Clock-data synchronization (CDS) in True-LVDS interface to
correct any fixed clock-to-data skew
– Enables common networking and communications bus I/O
standards such as RapidIO
TM
, CSIX, Utopia IV, and POS-PHY
Level 4
– Support for high-speed external memory interfaces, including
zero bus turnaround (ZBT), quad data rate (QDR), and double
data rate (DDR) static RAM (SRAM), and single data rate (SDR)
and DDR synchronous dynamic RAM (SDRAM)
–30% to 40% faster design performance than APEX
TM
20KE
devices on average
– Enhanced 4,096-bit embedded system blocks (ESBs)
implementing first-in first-out (FIFO) buffers, Dual-Port+ RAM
(bidirectional dual-port RAM), and content-addressable
memory (CAM)
– High-performance, low-power copper interconnect
– Fast parallel byte-wide synchronous device configuration
– Look-up table (LUT) logic available for register-intensive
functions
■ High-density architecture
– 1,900,000 to 5,250,000 maximum system gates (see Table 1)
– Up to 67,200 logic elements (LEs)
– Up to 1,146,880 RAM bits that can be used without reducing
available logic
■ Low-power operation design
– 1.5-V supply voltage
– Copper interconnect reduces power consumption
– MultiVolt
TM
I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V
interfaces
– ESBs offer programmable power-saving mode
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