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TMS320C6455
www.ti.com
SPRS276K–MAY 2005–REVISED FEBRUARY 2011
TMS320C6455
Fixed-Point Digital Signal Processor
Check for Samples: TMS320C6455
1 Features
12
• High-Performance Fixed-Point DSP (C6455) • Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
– 1.39-, 1.17-, 1-, and 0.83-ns Instruction Cycle
Time – 1.25-, 2.5-, 3.125-Gbps Link Rates
– 720-MHz, 850-MHz, 1-GHz, and 1.2-GHz Clock – Message Passing, DirectIO Support, Error
Rate Mgmt Extensions, Congestion Control
– Eight 32-Bit Instructions/Cycle – IEEE 1149.6 Compliant I/Os
– 9600 MIPS/MMACS (16-Bits) • DDR2 Memory Controller
– Commercial Temperature [0°C to 90°C] – Interfaces to DDR2-533 SDRAM
– Extended Temperature [-40°C to 105°C] – 32-Bit/16-Bit, 533-MHz (data rate) Bus
• TMS320C64x+™ DSP Core – 512M-Byte Total Addressable External
Memory Space
– Dedicated SPLOOP Instruction
• EDMA3 Controller (64 Independent Channels)
– Compact Instructions (16-Bit)
• 32-/16-Bit Host-Port Interface (HPI)
– Instruction Set Enhancements
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
– Exception Handling
Interconnect (PCI) Master/Slave Interface
• TMS320C64x+ Megamodule L1/L2 Memory
Conforms to PCI Local Bus Specification (v2.3)
Architecture:
• One Inter-Integrated Circuit (I
2
C) Bus
– 256K-Bit (32K-Byte) L1P Program Cache
• Two McBSPs
[Direct Mapped]
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– 256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative] – IEEE 802.3 Compliant
– 16M-Bit (2048K-Byte) L2 Unified Mapped – Supports Multiple Media Independent
RAM/Cache [Flexible Allocation] Interfaces (MII, GMII, RMII, and RGMII)
– 256K-Bit (32K-Byte) L2 ROM – 8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
– Time Stamp Counter
• Two 64-Bit General-Purpose Timers,
• Enhanced Viterbi Decoder Coprocessor (VCP2)
Configurable as Four 32-Bit Timers
– Supports Over 694 7.95-Kbps AMR
• UTOPIA
– Programmable Code Parameters
– UTOPIA Level 2 Slave ATM Controller
• Enhanced Turbo Decoder Coprocessor (TCP2)
– 8-Bit Transmit and Receive Operations up to
– Supports up to Eight 2-Mbps 3GPP
50 MHz per Direction
(6 Iterations)
– User-Defined Cell Format up to 64 Bytes
– Programmable Turbo Code and Decoding
• 16 General-Purpose I/O (GPIO) Pins
Parameters
• System PLL and PLL Controller
• Endianess: Little Endian, Big Endian
• Secondary PLL and PLL Controller, Dedicated
• 64-Bit External Memory Interface (EMIFA)
to EMAC and DDR2 Memory Controller
– Glueless Interface to Asynchronous
• Advanced Event Triggering (AET) Compatible
Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM, ZBT • Trace-Enabled Device
SRAM)
• IEEE-1149.1 (JTAG™)
– Supports Interface to Standard Sync Boundary-Scan-Compatible
Devices and Custom Logic (FPGA, CPLD,
• 697-Pin Ball Grid Array (BGA) Package
ASICs, etc.)
(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch
– 32M-Byte Total Addressable External
• 0.09-μm/7-Level Cu Metal Process (CMOS)
Memory Space
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 16
- ・ Abmessungen des Paketumrisses on Seite 251
- ・ Blockdiagramm on Seite 4 Seite 79 Seite 83 Seite 148 Seite 171
- ・ Beschreibung der Funktionen on Seite 55 Seite 56 Seite 57
- ・ Technische Daten on Seite 97 Seite 102 Seite 103 Seite 104 Seite 105
- ・ Anwendungsbereich on Seite 216 Seite 255
- ・ Elektrische Spezifikation on Seite 74 Seite 99 Seite 100 Seite 102 Seite 103
- ・ Teilenummernliste on Seite 8
