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THS8200
SLES032E –JUNE 2002–REVISED SEPTEMBER 2014
THS8200 All-Format Oversampled Component Video/PC Graphics D/A System With Three
11-Bit DACs, CGMS Data Insertion
1 Device Overview
1.1 Features
1
– Fully Programmable Display Timing Generator
• Overall
to Supply All SDTV and HDTV Composite Sync
– Three 11-Bit 205-MSPS Digital-to-Analog
Timing Formats, Progressive and Interlaced
Converters (DACs) With Integrated Bi-Level or
– Fully Programmable Hsync and Vsync Outputs
Tri-Level Sync Insertion
– Vertical Blanking Interval (VBI) Override or Data
– Support for All ATSC Video Formats (Including
Pass-Through for VBI Data Transparency
1080P) and PC Graphics Formats (up to UXGA
at 75 Hz) – Programmable CGMS Data Generation and
Insertion
• Input
• Output
– Flexible 10-, 15-, 16-, 20-, 24-, or 30-Bit Digital
Video Input Interface With Support for YCbCr or – Digital
RGB Data, Either 4:4:4 or 4:2:2 Sampled
• ITU-R BT.656 Digital Video Output Port
– Video Synchronization by Hsync or Vsync
– Analog
Dedicated Inputs or by Extraction of Embedded
• Analog Component Output from Software-
SAV and EAV Codes According to ITU-R.BT601
Switchable 700-mV or 1.3-V Compliant
(SDTV) or SMPTE 274M and SMPTE 296M
Output DACs at 37.5-Ω Load
(HDTV)
• Programmable Video/Sync Ratio (7:3 or
– Glueless Interface to TI DVI 1.0 (With HDCP)
10:4)
Receivers. Can Receive Video-Over-DVI
• Programmable Video Pedestal
Formats According to the EIA-861 Specification
• General
and Convert to YPbPr or RGB Component
– Built-In Video Color Bar Test Pattern Generator
Formats With Separate Syncs or Embedded
– Fast Mode I
2
C Control Interface
Composite Sync.
– Configurable Master or Slave Timing Mode
• Video Processing
• Configuration Modes Allow the Device to Act
– Programmable Clip/Shift/Multiply Function for
as a Master Timing Source for Requesting
Operation With Full-Range or ITU-R.BT601
Data From, for Example, the Video Frame
Video Range Input Data
Buffer (Master Mode Only Available for PC
– Programmable Digital Fine-Gain Controller on
Graphics Output Modes).
Each Analog Output Channel, for Accurate
• Alternatively, the Device Can Slave to an
Channel Matching and Programmable White-
External Timing Master.
Balance Control
– DAC and Chip Power-Down Modes
– Built-In 4:2:2 to 4:4:4 Video Interpolation Filter
– Low-Power 1.8-V and 3.3-V Operation
– Built-In 2x Oversampling SDTV and HDTV
Interpolation Filter for Improved Video
– 80-Pin PowerPAD™ Plastic Quad Flatpack
Frequency Characteristic
Package With Efficient Heat Dissipation and
Small Physical Size
– Fully Programmable Digital Color Space
Conversion Circuit
1.2 Applications
• DVD Players • Personal Video Recorders
• Digital-TV, Interactive-TV, or Internet Set-Top • HDTV Display or Projection Systems
Boxes
• Digital Video Systems
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Verzeichnis
- ・ Abmessungen des Paketumrisses on Seite 92
- ・ Markierungsinformationen on Seite 92
- ・ Blockdiagramm on Seite 3
- ・ Beschreibung der Funktionen on Seite 24 Seite 25 Seite 26 Seite 27 Seite 28
- ・ Technische Daten on Seite 8 Seite 9 Seite 10 Seite 11 Seite 12
- ・ Anwendungsbereich on Seite 1 Seite 93 Seite 97
