herunterladen
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
OMAP-L137
www.ti.com
SPRS563G –SEPTEMBER 2008–REVISED JUNE 2014
OMAP-L137 Low-Power Applications Processor
1 OMAP-L137 Low-Power Applications Processor
1.1 Features
1
• Supports up to Four SP Additions Per Clock,
• Software Support
Four DP Additions Every 2 Clocks
– TI DSP/BIOS™
• Supports up to Two Floating-Point (SP or
– Chip Support Library and DSP Library
DP) Reciprocal Approximation (RCPxP) and
• Dual Core SoC
Square-Root Reciprocal Approximation
– 375- and 456-MHz ARM926EJ-S™ RISC MPU
(RSQRxP) Operations Per Cycle
– 375- and 456-MHz C674x VLIW DSP
– Two Multiply Functional Units
• ARM926EJ-S Core
• Mixed-Precision IEEE Floating Point Multiply
– 32-Bit and 16-Bit (Thumb®) Instructions
Supported up to:
– DSP Instruction Extensions
– 2 SP x SP -> SP Per Clock
– Single Cycle MAC
– 2 SP x SP -> DP Every Two Clocks
– ARM® Jazelle® Technology
– 2 SP x DP -> DP Every Three Clocks
– Embedded ICE-RT™ for Real-Time Debug
– 2 DP x DP -> DP Every Four Clocks
• ARM9™ Memory Architecture
• Fixed-Point Multiply Supports Two 32 x 32-
– 16KB of Instruction Cache
Bit Multiplies, Four 16 x 16-Bit Multiplies, or
Eight 8 x 8-Bit Multiplies per Clock Cycle,
– 16KB of Data Cache
and Complex Multiples
– 8KB of RAM (Vector Table)
– Instruction Packing Reduces Code Size
– 64KB of ROM
– All Instructions Conditional
• C674x Instruction Set Features
– Hardware Support for Modulo Loop
– Superset of the C67x+ and C64x+ ISAs
Operation
– Up to 3648 MIPS and 2736 MFLOPS C674x
– Protected Mode Operation
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
– Exceptions Support for Error Detection and
– 8-Bit Overflow Protection
Program Redirection
– Bit-Field Extract, Set, Clear
• 128KB of RAM Shared Memory
– Normalization, Saturation, Bit-Counting
• 3.3-V LVCMOS I/Os (Except for USB Interfaces)
– Compact 16-Bit Instructions
• Two External Memory Interfaces:
• C674x Two-Level Cache Memory Architecture
– EMIFA
– 32KB of L1P Program RAM/Cache
• NOR (8- or 16-Bit-Wide Data)
– 32KB of L1D Data RAM/Cache
• NAND (8- or 16-Bit-Wide Data)
– 256KB of L2 Unified Mapped RAM/Cache
• 16-Bit SDRAM with 128-MB Address Space
– Flexible RAM/Cache Partition (L1 and L2)
– EMIFB
• Enhanced Direct Memory Access Controller 3
• 32-Bit or 16-Bit SDRAM with 256-MB
(EDMA3):
Address Space
– 2 Transfer Controllers
• Three Configurable 16550-Type UART Modules:
– 32 Independent DMA Channels
– UART0 with Modem Control Signals
– 8 Quick DMA Channels
– Autoflow Control Signals (CTS, RTS) on UART0
– Programmable Transfer Burst Size
Only
• TMS320C674x Fixed- and Floating-Point VLIW
– 16-Byte FIFO
DSP Core
– 16x or 13x Oversampling Option
– Load-Store Architecture with Nonaligned
• LCD Controller
Support
• Two Serial Peripheral Interfaces (SPIs) Each with
– 64 General-Purpose Registers (32-Bit)
One Chip Select
– Six ALU (32- and 40-Bit) Functional Units
• Multimedia Card (MMC)/Secure Digital (SD) Card
• Supports 32-Bit Integer, SP (IEEE Single
Interface with Secure Data I/O (SDIO)
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 26 Seite 47 Seite 98
- ・ Abmessungen des Paketumrisses on Seite 219
- ・ Markierungsinformationen on Seite 219
- ・ Blockdiagramm on Seite 4 Seite 12 Seite 95 Seite 116 Seite 129
- ・ Technische Daten on Seite 52 Seite 56 Seite 57 Seite 58 Seite 59
- ・ Anwendungsbereich on Seite 1 Seite 2 Seite 3 Seite 4 Seite 76
- ・ Elektrische Spezifikation on Seite 55 Seite 56 Seite 57 Seite 58 Seite 59
