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OMAP3530, OMAP3525
www.ti.com
SPRS507H –FEBRUARY 2008–REVISED OCTOBER 2013
OMAP3530 and OMAP3525 Applications Processors
Check for Samples: OMAP3530, OMAP3525
1 OMAP3530 and OMAP3525 Applications Processors
1.1 Features
12
• Protected Mode Operation
• OMAP3530 and OMAP3525 Devices:
• Exceptions Support for Error Detection
– OMAP™ 3 Architecture
and Program Redirection
– MPU Subsystem
• Hardware Support for Modulo Loop
• Up to 720-MHz ARM® Cortex™-A8 Core
Operation
• NEON™ SIMD Coprocessor
• C64x+ L1 and L2 Memory Architecture
– High-Performance Image, Video, Audio
– 32KB of L1P Program RAM and Cache
(IVA2.2™) Accelerator Subsystem
(Direct Mapped)
• Up to 520-MHz TMS320C64x+™ DSP Core
– 80KB of L1D Data RAM and Cache (2-Way
• Enhanced Direct Memory Access (EDMA)
Set-Associative)
Controller (128 Independent Channels)
– 64KB of L2 Unified Mapped RAM and Cache
• Video Hardware Accelerators
(4-Way Set-Associative)
– PowerVR® SGX™ Graphics Accelerator
– 32KB of L2 Shared SRAM and 16KB of L2
(OMAP3530 Device Only)
ROM
• Tile-Based Architecture Delivering up to
• C64x+ Instruction Set Features
10 MPoly/sec
– Byte-Addressable (8-, 16-, 32-, and 64-Bit
• Universal Scalable Shader Engine: Multi-
Data)
threaded Engine Incorporating Pixel and
– 8-Bit Overflow Protection
Vertex Shader Functionality
– Bit Field Extract, Set, Clear
• Industry Standard API Support:
– Normalization, Saturation, Bit-Counting
OpenGLES 1.1 and 2.0, OpenVG1.0
– Compact 16-Bit Instructions
• Fine-Grained Task Switching, Load
Balancing, and Power Management – Additional Instructions to Support Complex
Multiplies
• Programmable High-Quality Image Anti-
Aliasing • ARM Cortex-A8 Core
– Fully Software-Compatible with C64x and – ARMv7 Architecture
ARM9™
• TrustZone®
– Commercial and Extended Temperature
• Thumb®-2
Grades
• MMU Enhancements
• Advanced Very-Long-Instruction-Word (VLIW)
– In-Order, Dual-Issue, Superscalar
TMS320C64x+ DSP Core
Microprocessor Core
– Eight Highly Independent Functional Units
– NEON Multimedia Architecture
• Six ALUs (32- and 40-Bit), Each Supports
– Over 2x Performance of ARMv6 SIMD
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
– Supports Both Integer and Floating-Point
Arithmetic per Clock Cycle
SIMD
• Two Multipliers Support Four 16 x 16-Bit
– Jazelle® RCT Execution Environment
Multiplies (32-Bit Results) per Clock
Architecture
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
– Dynamic Branch Prediction with Branch
Results) per Clock Cycle
Target Address Cache, Global History
– Load-Store Architecture with Nonaligned
Buffer, and 8-Entry Return Stack
Support
– Embedded Trace Macrocell (ETM) Support
– 64 32-Bit General-Purpose Registers
for Noninvasive Debug
– Instruction Packing Reduces Code Size
• ARM Cortex-A8 Memory Architecture:
– All Instructions Conditional
– 16-KB Instruction Cache (4-Way Set-
– Additional C64x+ Enhancements
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2008–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 6 Seite 14
- ・ Abmessungen des Paketumrisses on Seite 259 Seite 260
- ・ Markierungsinformationen on Seite 259 Seite 260
- ・ Blockdiagramm on Seite 5 Seite 177 Seite 178 Seite 179
- ・ Beschreibung der Funktionen on Seite 196
- ・ Technische Daten on Seite 4 Seite 121 Seite 134 Seite 135 Seite 136
- ・ Anwendungsbereich on Seite 1 Seite 2 Seite 3 Seite 4 Seite 5
- ・ Elektrische Spezifikation on Seite 4 Seite 119 Seite 120 Seite 121 Seite 122
