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EV-ADF4356SD1Z User Guide
UG-1062
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADF4356 Microwave Wideband Synthesizer with Integrated VCO
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. A | Page 1 of 13
FEATURES
Self contained board, including ADF4356 frequency
synthesizer with integrated VCO, differential, 122.88 MHz,
temperature controlled crystal oscillator (TCXO), loop
filter (80 kHz), USB interface, and voltage regulators
Windows-based software allows control of synthesizer
functions from a PC
Externally powered by 5.5 V
EVALUATION KIT CONTENTS
EV-ADF4356SD1Z
EQUIPMENT NEEDED
Windows-based PC with USB port for evaluation software
System demonstration platform, serial only (SDP-S)
EVAL-SDP-CS1Z controller board
USB cable (included with the EVAL-SDP-CS1Z)
Power supply (5.5 V)
Spectrum analyzer
50 Ω terminators
ONLINE RESOURCES
Documents Needed
ADF4356 data sheet
EV-ADF4356SD1Z user guide
PLL Software Installation Guide
Required Software
Analog Devices, Inc., ADF4356 software, Version 1.0.10 or
higher
GENERAL DESCRIPTION
The EV-ADF4356SD1Z evaluates the performance of the ADF4356
frequency synthesizer with an integrated voltage control (VCO) for
phase-locked loops (PLLs). The evaluation board contains the
ADF4356 frequency synthesizer with an integrated VCO, a
differential 122.88 MHz reference (TCXO), a loop filter, a USB
interface, power supply connectors, and subminiature Version A
(SMA) connectors. A USB cable is included to connect the
board to a PC USB port.
This board requires an SDP-S (shown in Figure 1, but not supplied
with the kit). The SDP-S allows software programming of the
EV-ADF4356SD1Z.
When working with the evaluation board and for full
specifications of the device, consult the ADF4356 frequency
synthesizer data sheet. For easy programming of the
synthesizer, download the Windows®-based software from the
ADF4356 product page.
EVALUATION BOARD PHOTOGRAPH
15087-001
Figure 1.
