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MAX 10 FPGA Device Architecture
2016.05.13
M10-ARCHITECTURE
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The MAX
®
10 devices consist of the following:
• Logic array blocks (LABs)
• Analog-to-digital converter (ADC)
• User flash memory (UFM)
• Embedded multiplier blocks
• Embedded memory blocks (M9K)
• Clocks and phase-locked loops (PLL)
• General purpose I/O
• High-speed LVDS I/O
• External memory interfaces
• Configuration flash memory (CFM)
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Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 147 Seite 247 Seite 356 Seite 358 Seite 421
- ・ Blockdiagramm on Seite 7 Seite 16 Seite 30 Seite 41 Seite 153
- ・ Typisches Anwendungsschaltbild on Seite 6
- ・ Beschreibung der Funktionen on Seite 339 Seite 361 Seite 362 Seite 367 Seite 373
- ・ Technische Daten on Seite 230 Seite 289 Seite 475 Seite 476 Seite 518
- ・ Anwendungsbereich on Seite 177
