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Application Note 1767
ISL9000A Evaluation Board User Guide
Description
The ISL9000A Evaluation Board is designed to provide a
complete platform for demonstrating the performance of the
ISL9000A Low Dropout Regulator IC (LDO). It is designed to
show the small space required for all the components, while
providing room to access the signals.
The layout is intended to minimize thermal effects, to better
evaluate current limits and voltage regulation accuracy. In an
actual implementation, the area for heat sinking may be
smaller, so thermal effects may make the operation slightly
different.
The ISL9000A evaluation board constitutes a complete dual
voltage regulator solution. The PCB board is 2 inches by 3
inches, however, the actual charger components easily fit
within a 0.9x1.6 cm area (components on one side),
demonstrating the space saving advantage of the ISL9000A in
limited space applications.
A voltage source can be connected to the two pin connector
(J2, default) or to the banana jacks (not populated). For
monitoring the output, test instruments can be connected to
the five pin connector (J13, default) or to the banana jacks or
scope probe jacks (not populated). Additional test points
provide a convenient way to monitor the POR outputs and the
signal on the bypass capacitor. This can be especially
important when testing the LDO in a temperature chamber.
Several ground pins provide reference points for test leads.
Additional “kelvin” test points are provided for VIN, VO1, VO2,
and GND to monitor the actual performance of the IC. This
removes the voltage drops across the PCB traces that occurs
at higher currents.
The board has a jumper block for enabling each of the two LDO
outputs. A shunt can be placed on J3 or J4 between “ENx” and
“LOW” pins to provide a 100kΩ pull-down on each EN pin of
the device. If J3 or J4 ”HI” pins are floating, the respective LDO
output will be off, while connecting “HI” to “ENx” will enable
the output.
When it is desired that an LDO always be enabled, connect a
shunt between “ENx” and “HI” on J3 or J4. In this case the
shunt between “ENx” and “LOW” is not needed.
If an external enable signal that drives both high and low is
used to enable the LDO outputs, both shunts can be removed
from ENx.
A jumper (J10) connects the CPOR input to a 10nF capacitor
for POR timing. The jumper can be removed and replaced by a
different capacitor to ground for different power on timing
requirements.
The board also provides a connector (JP1, not populated)
which can connect to a logic analyzer/pattern generator for
controlling and monitoring the output response. The connector
provides both enable inputs and POR outputs.
Finally, a daughter card connector and a jumper (J14 and J9,
not populated) allow specially assembled boards containing
untrimmed LDOs to be programmed to custom voltage levels
after board assembly. This is done at the factory, so no
additional information will be provided in this document.
Ordering Information
PART
NUMBER
VO1 VOLTAGE
(V)
VO2 VOLTAGE
(V)
ISL9000AIRNNZ-EVZ 3.3 3.3
ISL9000AIRNJZ-EVZ 3.3 2.8
ISL9000AIRNFZ-EVZ 3.3 2.5
ISL9000AIRNCZ-EVZ 3.3 1.8
ISL9000AIRMNZ-EVZ 3.0 3.3
ISL9000AIRMMZ-EVZ 3.0 3.0
ISL9000AIRMGZ-EVZ 3.0 2.7
ISL9000AIRLLZ-EVZ 2.9 2.9
ISL9000AIRKNZ-EVZ 2.85 3.3
ISL9000AIRKKZ-EVZ 2.85 2.85
ISL9000AIRKJZ-EVZ 2.85 2.8
ISL9000AIRKFZ-EVZ 2.85 2.5
ISL9000AIRKPZ-EVZ 2.85 1.85
ISL9000AIRKCZ-EVZ 2.85 1.8
ISL9000AIRJNZ-EVZ 2.8 3.3
ISL9000AIRJMZ-EVZ 2.8 3.0
ISL9000AIRJRZ-EVZ 2.8 2.6
ISL9000AIRJCZ-EVZ 2.8 1.8
ISL9000AIRJBZ-EVZ 2.8 1.5
ISL9000AIRGPZ-EVZ 2.7 1.85
ISL9000AIRGCZ-EVZ 2.7 1.8
ISL9000AIRFJZ-EVZ 2.5 2.8
ISL9000AIRFDZ-EVZ 2.5 2.0
ISL9000AIRFCZ-EVZ 2.5 1.8
ISL9000AIRPLZ-EVZ 1.85 2.9
ISL9000AIRPPZ-EVZ 1.85 1.85
ISL9000AIRCJZ-EVZ 1.8 2.8
ISL9000AIRCCZ-EVZ 1.8 1.8
ISL9000AIRBLZ-EVZ 1.5 2.9
ISL9000AIRBJZ-EVZ 1.5 2.8
ISL9000AIRBCZ-EVZ 1.5 1.8
ISL9000AIRBBZ-EVZ 1.5 1.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright Intersil Americas Inc. 2012. All Rights Reserved.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
June 27, 2012
AN1767.0
Verzeichnis
- ・ Teilenummerierungssystem on Seite 1
- ・ Blockdiagramm on Seite 3
- ・ Teilenummernliste on Seite 2
