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Application Report
SLLA351 – December 2014
1
10GBASE-KR Link Optimization with TLK10034 and
TLK10232
Markus Zehendner Communications Interface
ABSTRACT
This application report highlights the 10 Gigabit Ethernet KR features of TI’s TLK10034 and
TLK10232 transceivers. The report provides information on 10GBASE-KR in general, important
registers of the TLK devices, how to set up a BER test, how to optimize a given 10GBASE-KR
link, and how to interpret test data provided by the devices.
Contents
1 About 10GBASE-KR, Auto Negotiation, and Link Training ....................................................... 2
1.1 What Happens When Auto Negotiation is Active?................................................................... 2
1.2 What Happens When Link Training is Activated? ................................................................... 2
2 General Requirements for 10GBASE-KR Applications .............................................................. 3
3 Setting up Tests and Measuring BER ......................................................................................... 3
3.1 High Speed (HS) Test ............................................................................................................. 4
3.2 Low Speed (LS) Test .............................................................................................................. 5
4 Important Parameters, Registers and bits for Link Optimization .............................................. 6
4.1 Transmitter Side ..................................................................................................................... 6
4.2 Receiver Side ......................................................................................................................... 8
5 Settings Which Influence Link Training Behavior .................................................................... 10
6 Evaluation of Link Training Results to Quantify Link Margin.................................................. 11
7 Link Down Issues and Solving Them ........................................................................................ 12
8 References .................................................................................................................................. 12
Figures
Figure 1. Block Diagram of the DFE and FFE Implementation on the Receiver Side of
TLK10034 and TLK10232 ................................................................................................. 9
Tables
Table 1. Bit Patterns for Different Test Patterns Available in the Vendor Space ....................... 4
Table 2. Bit Patterns for Different Test Patterns From the PCS Layer ....................................... 4
Table 3. SWING bit Patterns and Corresponding Amplitude Values in mVdpp, Device
Address 0x1E, Register 0x0003, bits [15:12].................................................................. 6
Table 4. PRE-CURSOR bit Patterns and Corresponding Tap Weights in %, Device Address
0x1E, Register 0x0005, bits [7:4]..................................................................................... 7
Table 5. POST-CURSOR 1 bit Patterns and Corresponding Tap Weights in %, Device
Address 0x1E, Register 0x0005, bits [12:8] ................................................................... 7
Table 6. Equalizer bit Patterns, EQPRE Values and Corresponding FIR Coefficients .............. 8
