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1. General description
The ISP1760 is a Hi-Speed Universal Serial Bus (USB) host controller with a generic
processor interface. It integrates one Enhanced Host Controller Interface (EHCI), one
Transaction Translator (TT) and three transceivers. The host controller portion of the
ISP1760 and the three transceivers comply to Ref. 1 “
Universal Serial Bus Specification
Rev. 2.0”. The EHCI portion of the ISP1760 is adapted from Ref. 2 “Enhanced Host
Controller Interface Specification for Universal Serial Bus Rev. 1.0”.
The integrated high-performance Hi-Speed USB transceivers enable the ISP1760 to
handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s). The three downstream ports allow simultaneous
connection of three devices at different speeds (high-speed, full-speed and low-speed).
The generic processor interface allows the ISP1760 to be connected to various
processors as a memory-mapped resource. The ISP1760 is a slave host: it does not
require ‘bus-mastering’ capabilities of the host system bus. The interface can be
configured, ensuring compatibility with a variety of processors. Data transfer can be
performed on 16 bits or 32 bits, using Programmed Input/Output (PIO) or Direct Memory
Access (DMA) with major control signals configurable as active LOW or active HIGH.
Integration of the TT allows connection to full-speed and low-speed devices, without the
need of integrating Open Host Controller Interface (OHCI) or Universal Host Controller
Interface (UHCI). Instead of dealing with two sets of software drivers, EHCI and OHCI or
UHCI, you need to deal with only one set, EHCI, that dramatically reduces software
complexity and IC cost.
2. Features
The host controller portion of the ISP1760 complies with Ref. 1 “Universal Serial Bus
Specification Rev. 2.0”
The EHCI portion of the ISP1760 is adapted from Ref. 2 “Enhanced Host Controller
Interface Specification for Universal Serial Bus Rev. 1.0”
Contains three integrated Hi-Speed USB transceivers that support high-speed,
full-speed and low-speed modes
Integrates a TT for Original USB (full-speed and low-speed) device support
Up to 64 kB internal memory (8 k × 64 bits) accessible through a generic processor
interface; operation in multitasking environments is made possible by the
implementation of virtual segmentation mechanism with bank switching on task
request
Generic processor interface, non-multiplexed and variable latency, with a configurable
32-bit or 16-bit external data bus; the processor interface can be defined as
variable-latency or SRAM type (memory mapping)
ISP1760
Hi-Speed USB host controller for embedded applications
Rev. 08 — 13 April 2010 Product data sheet
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