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© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 1
1 Publication Order Number:
AND9114/D
AND9114/D
Maintaining Signal Integrity
when Selecting ESD
Protection for USB 3.0
Interface
Introduction
As today’s lifestyle becomes more content rich through
the use of streaming and sharing high quality video, photos,
and music; data transfer rates have risen to new levels to
keep up with the demand. High speed data rates are central
to our ability to consume, share, back up, and create or edit
content. With this increase in data transfer rates, chipset
feature sizes are getting smaller and smaller which means
the threat of Electrostatic Discharge (ESD) is more real now
than ever before. This Application Note will discuss the
challenges that designers are facing with regards to signal
integrity when selecting ESD protection products for
USB 3.0 and how ON Semiconductor’s solutions overcome
those challenges.
The Challenge to Preserve USB 3.0 Signal Quality
USB 3.0 is the latest revision in the Universal Serial Bus
(USB) standard which allows data transfer rates up to
5 Gbit/s, over 10 times the 480 Mbit/s speed of USB 2.0.
In order to achieve the 5 Gbit/s data rate, two differential
data pairs (SuperSpeed Tx and Rx) have been added to the
already existent USB 2.0 data pair, D+ and D−. In addition,
chipsets today that support USB 3.0 interfaces have process
geometries as low as 22 nm in order to support the fast data
rate. With the decrease in feature size of USB 3.0 compatible
chipsets, the SuperSpeed lines that carry the USB 3.0 data
signal become very sensitive to transients such as ESD. Not
only is it critical to suppress ESD transients on these lines,
it is also important to not degrade the quality of the USB 3.0
signal transmission. The increase in frequency, compared to
USB 2.0 transmission, creates a strict impedance matching
window that must be met when placing an external ESD
protection device on the SuperSpeed lines. Any small
amount of capacitance that is added to the signal line can
change its impedance and thus degrade the overall signal
integrity of the transmission. It is critical that designers
understand the important device parameters of ESD
protection products that can affect the impedance path of the
data line.
Capacitance
Figure 1 shows a circuit representation of a lossless
transmission line where the nominal impedance is
represented by Z
0
.
L
C
Where : Z
0
+
L
C
Ǹ
+ line impedance
Figure 1. Lossless Transmission Line − Equivalent
Circuit
This transmission line model can be applied to a high
speed data line present in almost any of today’s high speed
serial interfaces. The model can also be used to evaluate the
effect of placing an ESD protection device onto the data
line/s.
In its most basic form, an ESD protection device can be
viewed as a Zener diode placed on the data line it is to
protect. This zener diode has an associated junction
capacitance, along with a small amount of series inductance
from the internal bond wires in the package, which become
parasitic to the data line as shown in Figure 2. Since the
inductance of a typical wire bond in an ESD protection
device is typically 1 nH or less and the capacitance of the
ESD protection element must be 1 pF or below, the
impedance of the inductors in Figure 2 are always well
below the impedance of the capacitances at the 2.5 GHz
speed of the USB signal. For that reason the inductance will
be ignored in this discussion.
Figure 2. ESD Protection Device − Parasitic Model
APPLICATION NOTE
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