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CY8C20X36A/46A/66A/96A/46AS/66AS
1.8 V CapSense
®
Controller with
SmartSense™ Auto-tuning
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-54459 Rev. *L Revised December 13, 2011
CapSense
®
Applications
Features
■ Wide operating range: 1.71 V to 5.5 V
■ Ultra low deep sleep current: 100 nA
❐ Configurable capacitive sensing elements
❐ 7 μA per sensor at 500ms scan rate
❐ Supports SmartSense Auto-tuning
❐ Supports a combination of CapSense buttons, sliders,
touchpads, touchscreens, and proximity sensors
❐ SmartSense_EMC offers superior noise immunity for
applications with challenging conducted and radiated noise
conditions
■ Powerful Harvard-architecture processor
❐ M8C CPU – Up to 4 MIPS with 24 MHz Internal clock, external
crystal resonator or clock signal
❐ Low power at high speed
■ Temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ Three program/data storage size options:
• 8 KB flash/1 KB SRAM
• 16 KB flash/2 KB SRAM
• 32 KB flash/2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ Partial flash updates
❐ Flexible protection modes
❐ In-system serial programming (ISSP)
■ Full-speed USB
❐ 12 Mbps USB 2.0 compliant
■ Precision, programmable clocking
❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5%
❐ Internal low speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ Precision 32 kHz oscillator for optional external crystal
■ Programmable pin configurations
❐ Up to 36 general-purpose I/Os (GPIOs) (depending on
package)
❐ Dual mode GPIO: All GPIOs support digital I/O and analog
inputs
❐ 25-mA sink current on each GPIO
• 120 mA total sink current on all GPIOs
❐ Pull-up, high Z, open-drain modes on all GPIOs
❐ CMOS drive mode –5 mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
• 20 mA total source current on all GPIOs
■ Versatile analog system
❐ Low-dropout voltage regulator for all analog resources
❐ Common internal analog bus enabling capacitive sensing on
all pins
❐ High power supply rejection ratio (PSRR) comparator
❐ 8 to 10-bit incremental analog-to-digital converter (ADC)
■ Additional system resources
❐ I
2
C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
❐ Emulated E2PROM using flash memory
■ Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Versatile package options
❐ 16-pin 3 × 3 × 0.6 mm QFN
❐ 24-pin 4 × 4 × 0.6 mm QFN
❐ 32-pin 5 × 5 × 0.6 mm QFN
❐ 48-pin SSOP
❐ 48-pin 7 × 7 × 1.0 mm QFN
❐ 30-ball WLCSP
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 9 Seite 10 Seite 11 Seite 12 Seite 13
- ・ Abmessungen des Paketumrisses on Seite 34 Seite 35 Seite 36 Seite 37
- ・ Teilenummerierungssystem on Seite 41 Seite 42 Seite 43
- ・ Blockdiagramm on Seite 2 Seite 4
- ・ Schweißen Temperatur on Seite 38
- ・ Beschreibung der Funktionen on Seite 41 Seite 42 Seite 43
- ・ Technische Daten on Seite 19 Seite 20 Seite 21 Seite 22 Seite 23
- ・ Anwendungsbereich on Seite 1
- ・ Elektrische Spezifikation on Seite 19 Seite 24
